1 ps8628 03/23/01 oeab clkenab clkab leab leba clkba clkenba oeba a1 3 27 29 30 28 2 55 56 1 ce 1d c1 clk ce 1d c1 clk b1 54 to 17 other channels product description pericom semiconductor?s pi74avc+ series of logic circuits are produced using the company?s advanced submicron cmos technology, achieving industry leading speed. the pi74avc+16601 uses d-type latches and d-type flip-flops with 3-state outputs to allow data flow in transparent, latched, and clocked modes. data flow in each direction is controlled by output enable (oeab and oeba), latch enable (leab and leba), and clock (clkab and clkba) inputs. the clock can be controlled by the clock enable (clkenab and clkenba) inputs. for a-to-b data flow, the device operates in the transparent mode when leab is high. when leab is low, the a data is latched if clkab is held at a high or low logic level. if leab is low, the a-bus is stored in the latch/flip-flop on the low-to-high transition of clkab. output enable oeab is active low. when oeab is low, the outputs are active. when oeab is high, the outputs are in the high-impedance state. data flow for b to a is similar to that of a to b but uses oeba, leba, clkba, and clkenba. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16601 2.5v 18-bit universal bus transceiver with 3-state outputs logic block diagram product features ? pi74avc+16601 is designed for low-voltage operation, v cc = 1.65v to 3.6v ? true 24ma balanced drive @ 3.3v ? i off supports partial power-down operation ? 3.6v i/o tolerant inputs and outputs ? all outputs contain a patented ddc (dynamic drive control) that reduces noise without degrading propagation delay. ? industrial operation: ?40c to +85c ? available packages: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 173 mil wide plastic tvsop (k)
2 ps8628 03/23/01 pi74avc+16601 2.5v 18-bit universal bus transceiver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pin description truth table (1) ? pin configuration oeab leab a1 gnd a2 a3 v cc a4 a5 a6 gnd a7 a8 a9 a10 a11 a12 gnd a13 a14 a15 v cc a16 a17 gnd a18 oeba leba 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 clkenab clkab b1 gnd b2 b3 v cc b4 b5 b6 gnd b7 b8 b9 b10 b11 b12 gnd b13 b14 b15 v cc b16 b17 gnd b18 clkba clkenba 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56-pin a,k s t u p n i t u p t u o b b a n e k l cb a e ob a e lb a k l ca xhxxxz xlhxll xlhshh hllxxb 0 ? hllxxb 0 ? lll - ll lll - hh lll h r o lxb 0 ? notes: 1. h = high signal level l = low signal level z = high impedance - = low-to-high transition ? a-to-b data flow is shown: b-to-a flow is similar but uses oeba, leba, clkba, and clkenba. ? output level before the indicated steady-state input conditions were established. e m a n n i pn o i t p i r c s e d e o) w o l e v i t c a ( t u p n i e l b a n e t u p t u o k l c) h g i h e v i t c a ( t u p n i k c o l c d x s t u p n i a t a d q x s t u p t u o e t a t s - 3 d n gd n u o r g v c c r e w o p
pi74avc+16601 2.5v 18-bit universal bus transceiver with 3-state outputs 3 ps8628 03/23/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 recommended operating conditions (1) notes: 1. all unused inputs must be held at v cc or gnd to ensure proper device operation. . n i m. x a ms t i n u v c c e g a t l o v y l p p u s g n i t a r e p o5 6 . 16 . 3 v y l n o n o i t n e t e r a t a d2 . 1 v h i e g a t l o v t u p n i l e v e l - h g i h v c c v 2 . 1 =v c c v c c v 5 9 . 1 o t v 5 6 . 1 =x 5 6 . 0v c c v c c v 7 . 2 o t v 3 . 2 =7 . 1 v c c v 6 . 3 o t v 3 =2 v l i e g a t l o v t u p n i l e v e l - w o l v c c v 2 . 1 =d n g v c c v 5 9 . 1 o t v 5 6 . 1 =x 5 3 . 0v c c v c c v 7 . 2 o t v 3 . 2 =7 . 0 v c c v 6 . 3 o t v 3 =8 . 0 v i e g a t l o v t u p n i 06 . 3 v o e g a t l o v t u p t u o e t a t s e v i t c a0v c c e t a t s - 306 . 3 i h o t n e r r u c t u p t u o l e v e l - h g i h v c c v 5 9 . 1 o t v 5 6 . 1 =6 ? a m v c c v 7 . 2 o t v 3 . 2 =2 1 ? v c c v 6 . 3 o t v 3 =4 2 ? i l o t n e r r u c t u p t u o l e v e l - w o l v c c v 5 9 . 1 o t v 5 6 . 1 =6 v c c v 7 . 2 o t v 3 . 2 =2 1 v c c v 6 . 3 o t v 3 =4 2 d t d e t a r l l a f r o e s i r n o i t i s n a r t t u p n i vv c c v 6 . 3 o t v 5 6 . 1 =5v / s n t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o 0 4 ?5 8c note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating onl y and functional operation of the device at these or any other conditions above those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) supply voltage range, v cc ............................................ ?0.5v to +4.6v input voltage range, v i ................................................... ?0.5v to +4.6v voltage range applied to any output in the high-impedance or power-off state, v o (1) ........... ?0.5v to +4.6v voltage range applied to any output in the high or low state, v o (1,2) .................................... ?0.5v to v cc +0.5v input clamp current, i ik (v i <0) ......................................... ?50ma notes: 1. input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. output positive-voltage rating may be exceeded up to 4.6v maximum if theoutput current rating is observed. 3. the package thermal impedance is calculated in accordance with jesd 51. output clamp current, i ok (v o <0) .................................... ?50ma continuous output current, i o ..................................................... 50ma continuous current through each v cc or gnd ............... 100ma package thermal impedance, q ja (3) : package a .............. 64c/w package k ...................... 48c/w storage temperature range, t stg ................................. ?65c to 150c
4 ps8628 03/23/01 pi74avc+16601 2.5v 18-bit universal bus transceiver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a ps n o i t i d n o c t s e t ) 1 ( v c c . n i m. x a ms t i n u v h o i h o 0 0 1 ? =a v 6 . 3 o t v 5 6 . 1v c c v 2 . 0 ? v i h o 6 ? =m v a h i v 7 0 . 1 =v 5 6 . 12 . 1 i h o 2 1 ? =m v a h i v 7 . 1 =v 3 . 25 7 . 1 i h o 4 2 ? =m v a h i v 2 =v 30 . 2 v l o i l o 0 0 1 =a v 6 . 3 o t v 5 6 . 12 . 0 i l o 6 =m v a h i v 7 5 . 0 =v 5 6 . 15 4 . 0 i l o 2 1 =m v a h i v 7 . 0 =v 3 . 25 5 . 0 i l o 4 2 =m v a h i v 8 . 0 =v 38 . 0 i i s t u p n i l o r t n o cv i v = c c d n g r ov 6 . 35 . 2 a i f f o v i v r o o v 6 . 3 =00 1 i z o v i v = c c d n g r ov 6 . 30 1 i c c v o v = c c i d n g r o o 0 =v 6 . 30 4 c i s t u p n i l o r t n o cv i v = c c d n g r ov 5 . 24 f p v 3 . 34 s t u p n i a t a dv 5 . 26 v 3 . 36 c o s t u p t u ov o v = c c d n g r ov 5 . 28 v 3 . 38 note: 1. typical values are measured at t a = 25c. dc electrical characteristics (over the operating range, t a = ?40c +85c)
pi74avc+16601 2.5v 18-bit universal bus transceiver with 3-state outputs 5 ps8628 03/23/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v c c v 2 . 1 = v c c v 5 . 1 = v 1 . 0 v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u . n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m f x a m 0 5 10 5 20 5 3z h m t d p b r o aa r o b5 . 40 . 45 . 30 . 35 . 2 s n r o b a e l a b e l b r o a 0 . 55 . 40 . 45 . 30 . 3 r o b a k l c a b k l c 5 . 55 . 40 . 45 . 30 . 3 t n e r o b a e o a b e o 5 . 40 . 40 . 45 . 30 . 3 t s i d 5 . 50 . 40 . 40 . 30 . 3 timing requirements (over recommended operating free-air temperature range, unless otherwise noted, see figures 1 thru 4) switching characteristics (over recommended operating free-air temperature range, unless otherwise noted, see figures 1 thru 4) operating characteristics, t a = 25c s r e t e m a r a p t s e t s n o i t i d n o c v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u l a c i p y tl a c i p y tl a c i p y t c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p d e l b a n e s t u p t u o c l , f p 0 = z h m 0 1 = f 2 26 20 3 f p d e l b a s i d s t u p t u o 568 v c c v 2 . 1 = v c c v 5 . 1 = v 1 . 0 v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u . n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m f k c o l c y c n e u q e r f k c o l c 0 5 10 5 20 5 3z h m t w e s l u pn o i t a r u dh g i h e l3 . 30 . 25 . 1 s n w o l r o h g i h k l c3 . 30 . 25 . 1 t u s e m i t p u t e sk l c e r o f e b a t a d - 5 . 35 . 20 . 29 . 15 . 1 a t a d e l e r o f e b h g i h k l c2 . 12 . 12 . 12 . 14 . 1 w o l k l c0 . 10 . 11 . 11 . 19 . 0 k l c e r o f e b n e k l c - 0 . 30 . 25 . 15 . 12 . 1 t h d l o he m i t k l c r e t f a a t a d - 00 1 . 05 . 06 . 0 a t a d e l r e t f a h g i h k l c2 . 12 . 12 . 12 . 12 . 1 w o l k l c3 . 27 . 17 . 17 . 15 . 1 k l c r e t f a n e k l c - 00 4 . 04 . 04 . 0
6 ps8628 03/23/01 pi74avc+16601 2.5v 18-bit universal bus transceiver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 1.2v and 1.5v 0.1v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 1. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times
pi74avc+16601 2.5v 18-bit universal bus transceiver with 3-state outputs 7 ps8628 03/23/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 1.8v 0.15v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 2. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 1 k w 1 k w 0.15v 0.15v 30
8 ps8628 03/23/01 pi74avc+16601 2.5v 18-bit universal bus transceiver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 2.5v 0.2v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 3. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.15v C0.15v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 w 500 w 30
pi74avc+16601 2.5v 18-bit universal bus transceiver with 3-state outputs 9 ps8628 03/23/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 3.3v 0.3v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 4. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 w 500 w 0.3v 0.3v 30 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com
10 ps8628 03/23/01 pi74avc+16601 2.5v 18-bit universal bus transceiver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 56-pin tssop (a) package 56-pin tvsop (k) package a t a d g n i r e d r on o i t p i r c s e d a 1 0 6 6 1 + c v a 4 7 i p p o s s t c i t s a l p e d i w l i m - 0 4 2 , n i p - 6 5 k 1 0 6 6 1 + c v a 4 7 i p p o s v t c i t s a l p e d i w l i m - 3 7 1 , n i p - 6 5 .047 .031 .041 seating plane .016 bsc 1 56 .169 .177 11.20 11.40 4.30 4.50 1.20 0.40 0.13 0.23 0.80 1.05 x.xx x.xx denotes dimensions in millimeters .002 .006 0.05 0.15 .0035 .008 0.09 0.20 .018 .030 0.45 0.75 6.4 .252 bsc .005 .009 .441 .449 max. .002 .006 seating plane .007 .011 .004 .008 1 56 .236 .244 0.50 0.17 0.27 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 max. 1.20 6.0 6.2 .547 .555 13.9 14.1 .319 8.1 .0197 bsc bsc ordering information
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